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Clock Divider - any info needed

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RTL2GDSII

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Clock Divider

Any info about how to generate a non-integer clock divider.
Like Clk_out = Clk_in x (N/M), N and M are integer.
Thanks !
 

penrico

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Use a PLL to multiply your frequency (N), then use a logic divider to divide the multiplied frecuency (M).




Fin--> Phase Comp ---> Filter ---> VCO +--> Divider M ----> Fout=FxN/M
.................^........................................|
..................|<---------Divider N----------+
 

RTL2GDSII

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Any digital PLL information ?
 

penrico

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What is your base frequency?, so what is your final frequency?

If you have a highter clock than base frequency (about 10 times base frequency or more), using a CPLD you can improve a digital PLL to multiply the base frequency.
 

DrBELL

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Clock Divider

Hi,

See if this article is of use to you. It talks
about Unsual Clock Division Requirements


DrBELL
 

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