Clock Divider - any info needed

[RTL2GDSII]

Clock Divider

Any info about how to generate a non-integer clock divider.
Like Clk_out = Clk_in x (N/M), N and M are integer.
Thanks !

 

[penrico]

Use a PLL to multiply your frequency (N), then use a logic divider to divide the multiplied frecuency (M).




Fin--> Phase Comp ---> Filter ---> VCO +--> Divider M ----> Fout=FxN/M
.................^........................................|
..................|<---------Divider N----------+

 

[RTL2GDSII]

Any digital PLL information ?

 

[penrico]

What is your base frequency?, so what is your final frequency?

If you have a highter clock than base frequency (about 10 times base frequency or more), using a CPLD you can improve a digital PLL to multiply the base frequency.

 

[DrBELL]

Clock Divider

Hi,

See if this article is of use to you. It talks
about Unsual Clock Division Requirements


DrBELL

 

[Ignazio]

clock dividers

The doc "Unusual clock dividers" and others information are at this link:

http://www.parmita.com/verilogcenter/papers.html

Bye, I.