clock crossing: single gate between source and destination domain

[vijay82]

What could be the possible problem when the source data is unregistered and passes through a single gate, say a buffer, and then on to the destination 2-D synchronizer? As we know, the reason for registering source data is to prevent glitches from being caught by the destination. Here the gate will not suffer any such glitches, being a single primitive [i/w question]

 

[rca]

The question is more what drive the buffer in the source side?, combinational logic or flop?
if it is a combinational logic, that could generate a glitch and this one could cross the buffer and be catch by the destination flop.

 

[vijay82]

Just to make it clear: Source flop drives buffer drives destination flop (which is part of a 2D synchronizer).
Any ideas?

I'm pretty sure its not right to have that lone ranger buffer hanging in there, but cannot quite pinpoint why. The reason would most probably be concerned with something related to synthesis/P&R based issues (as opposed to logical).

 

[sharath666]

A problem could arise if individual data bits suffer widely differing routing delays. Or if the capacitive loading is different.

 

[ads-ee]

A problem could arise if individual data bits suffer widely differing routing delays. Or if the capacitive loading is different.

The OP is discussing a synchronizer. If you synchronize data bits (a bus) using a two stage synchronizer then my guess would be your designs have unexplained intermittent problems that show up in testing and production.

Regards

 

[vijay82]

sharath666, its just one bit being synchronized. That rules out different routing delays as a reason. Capacitive loading is out too I guess by the same yardstick.

When I answered that the buffer could consume an incoming pulse (which is the reason for specifying minimum pulse widths for signals passing through multiple buffers), it was countered by the interviewer with a new specification - that the buffer characteristics were akin to a clock buffer (by which I assume the rise/fall delays of the buffer are too less to affect the pulse).

 

[vijay82]

Would appreciate some brainstorming on this question. Its an interesting question in my opinion, besides being important if we are to really understand why combos are so bad between 2 async domains.

 

[rahul.achates]

I didn't go through all the replies .. but I know the issue.
1. CDC tool will issue a error on this , Its a rule where signal going from one clock to another clock domain, must not coming through combo logic.
2. Since you dont know when data will be captured in second clock domain , small delay may create an issue if latency is more important. also , if there are others signals which depend on this, then your functionality may changed ..

There are multiple reason why this should not follow .. and you need to understand each and every reason.