Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[Clock Constrain with Generated Clocks]

Status
Not open for further replies.

downloadman

Newbie level 6
Joined
Dec 22, 2008
Messages
14
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,381
Hi,

a) I have 4 primary clocks i.e clk1,clk2, clk3, clk4 to the design.
b) There are two muxes to which these primay clocks are input to the muxes and one of the mux outputs will be fed to a divider.
c) The divider output again is muxed with second Mux[First stage Mux] output.
d) The output of the second stage mux is again scan Muxed with Scan Clock. This is the final clock output whcih is fed to logic.

I have maintained the following approach :

a) Given create_clock constraints for all the primary clocks
b) Given set_Case_analysis for all the muxes and divider stages.
c) Given create_generated clock constrains for the mux outputs and divider output as follows :

create_generated_clock -name <MUX_FIRST_STAGE_OUTPUT> [get_pints <hierrarchy/MUX_FIRST_STAGE_INSTANTIATION/OutputPortName] -source [get_ports <primary_clock_name>] -divide by 1
d) Define clock latency, uncertainty common for all the clocks.

With this approach, we are getting very very bad timings in the reports:-(.

My assumption, is that as the clocks are defined as generated clock, we should define clock latency separately for each and every generated clocks.

How to give constraints for the above structure?

Thanks in Advance

---------- Post added at 05:46 ---------- Previous post was at 05:42 ----------

Hi,

Please not that the synthesis has to be carried out in Magma.

Regards
Murali
 

shitansh

Full Member level 5
Joined
Jan 6, 2009
Messages
296
Helped
50
Reputation
98
Reaction score
28
Trophy points
1,308
Location
India-Gujarat
Activity points
3,019
In case of multiplexer with clocks on both its inputs.it is not necessary to define a clock on the output of the multiplexer.

If the select signal is set to a constant, the output of the multiplexer automatically gets the correct clock propagated.

If the select pin of the multiplexer is unconstrained, both the clocks propagate through the multiplexer for the purposes of the STA.
In such cases, the STA may report paths between both input clocks i.e. clk_1 & clk_2.
Note that such paths are not possible as the select line can select only one of the multiplexer inputs.
In such a case, one may need to set a false path or specify an exclusive clock relationship between these two clocks to avoid incorrect paths being reported.
This of course assumes that there are no paths between both input clock of mux i.e. clk_1 & clk_2 elsewhere in the design.

If the multiplexer select signal is not static and changing during device operaton, then in such case clock gating check are inferred for the multiplexer inputs. These checks ensure that the clocks at the multiplexer inputs switch safely
with respect to the multiplexer select signal.

Now since the gating cell is a multiplexer, the clock gating check is not inferred automatically (you can check timing report to confirm).

However a clock gating check can be explicitly forced by providing a set_clock_gating_check specification.
e.g.
set_clock_gating_check -high [get_cells UMUX0]
Here, The -high option indicates an active-high check.

HTH,
Shitansh Vaghela
 

downloadman

Newbie level 6
Joined
Dec 22, 2008
Messages
14
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,381
Hi shitansh,

Thanks for the reply.
Your reply answers my first part of the question, by which i infer that I have to remove most the <create_generated_clocks> commands used to generate mux stage outputs. I will do that.

The second part of the question, where i have mentioned to provide the clock latency, for the clock outputs of the divider stages.
Can you please clarify on this?

I want to tell you the real problem is, that
a) if I remove all the mux logic and divider stages in the clock controller.
b) Primary Clocks going to Scan Muxes and connected to logic.
In the above approach, I have given constraints only for primary clocks.
With this experiment, my timing got very better when compared with clock controller with Logic.

Like with clock controller, the timing is about 2ns and without clockcontroller logic it is about 0.4ns :smile: .

I am stuck at this point, like how to give constraint for the complete clock controller with mux logic and divider stages and then mux logic etc.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top