Clock connected to the D input of the FF

[mr_vasanth]

In some of the designs, I have noticed a clock input is connected to the D input of the Flip Flop.
What could be the design scenario that would need these kind of connections ?

 

[kaiserschmarren87]

Have you got any example or design which has that connection ?

 

[ebuddy]

One example is that I2C slave design. The "START" condition is asserted when at SDA falling edge, SCL is high. This requires SCL, the "clock" signal be connected the the D-pin of a flip flop.

 

[kaiserschmarren87]

One example is that I2C slave design. The "START" condition is asserted when at SDA falling edge, SCL is high. This requires SCL, the "clock" signal be connected the the D-pin of a flip flop.

You mean like this for example ?

 

[FvM]

One example is that I2C slave design. The "START" condition is asserted when at SDA falling edge, SCL is high. This requires SCL, the "clock" signal be connected the the D-pin of a flip flop.

You'll do this may be in a small CPLD that has no suitable clock for synchronous processing of I2C signals. As an example, industry standard I2C peripherals are processing the bus signals in an asynchronous way.

There are also cases where you use "data as clock" in larger designs, e.g. in a toggle synchronizer. In timing analysis, the data will be considred as clock and must be respectively constrained.

 

[layowblue]

ebuddy, could you elaborate the I2C case?
In this case, if SCL is hooked to D-pin of a flop, which signals is driving the clk-pin of the flop?
And how is SDA possible used, or sampled?

Thanks
Leo