clock and reset design structure for SOC or Lower Power SOC

[lubee]

Hi, buddy

Do you have any books or papers about the latest clock and reset logic design for the current SOC which become more and more complex and will have all kinds of power domain.

For example, I came across a clock/reset problem in the real silicon:
I used PLL's stable signal as some clock dividers' reset which is the async-asserted and sync-deasserted. When PLL is shut down to save power, in this case, async-asserted reset may cause clock divider to generate clock glitch. But all the circuit under this PLL will be reset, it will take no effect on the function. However in current out SOC, it has so many kinds of power domain. When the PLL is shut down and some power domain still powered, the clock divider's clock glitch will cause circuit failed.

So do you have any comments or principals about designing the clock structure and reset structure/scheme? For example, sync-asserted reset should be used in the clock divider design. or something else?

 

[mail4idle2]

You put logic circuit in reset which is working on clock you have mentioned before shutting down PLL

 

[lubee]

thank you for your reply. in some cases, always-on power domain should keep their values so they should not be reset before the PLL shut down. I can gated these clock before the shut-down pll, after cpu is power up again and release them then. But this scheme needs SW to coordination.

 

[mail4idle2]

Check for any signal from pll itself before it shuts down (other than stable signal) to solve your problem

 

[prassingh]

I don't think using up of PLL stable signal as a reset is good design methodology. When you would be doing dynamic frequency change in a PLL the stable signal would be toggling and this would lead to reset assertion/deassertion, which you don't want.
So better way would be to create a reset logic that would use up the signal from PMC(power management controller) which would be probably used to power down pLL (depends on chip arch) and synchronize it with root clock using a synchronizer and then apply the reset.