clock and data recovery - FPGA design needed

[vinod_g]

clock and data recovery

I require CDR( Clock and data recovery) module. Is it already available in FPGA or we have to design?

 

[ducna]

Re: clock and data recovery

I am familar with Xilinx, so I have no idea for other families, but i think they are quite the same. In Xilinx, the is no integrated CDR part; however, luckily there are some App Notes such as : xapp224, xapp250, xapp868, ... very usuful for CDR applications. Also, you can check on the Internet with google, there is a lot of information for you

Hope this helps,

 

[amitjagtap]

clock and data recovery

hi
In some FPGA CDR is there. In Xilinx FPGA Clock managers are there. U can design a simple clk n data recovery ckt using edge detector and high frequency counter....