pavan.prakash
Newbie level 4
Hi,
I want to design a clock and data recovery circuit at 7gbps using 65nm technology. which cdr model is best to design? Is it the single loop or dual loop one? I need a phase frequency detector and i thought of designing binary detector. Please help me with it? and help me if there is any paper available.
Thank you.
I want to design a clock and data recovery circuit at 7gbps using 65nm technology. which cdr model is best to design? Is it the single loop or dual loop one? I need a phase frequency detector and i thought of designing binary detector. Please help me with it? and help me if there is any paper available.
Thank you.