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Class in system verilog

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sunidrak

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Can anybody plz explain the difference and meaning of the two Code Snippet highlighted...


code -1



class base;
task print();
........
endtask
endclass
class derived extends base;
task print();
........
endtask
endclass

module main();
base b; //Instance
derived d; //Instance
initial
begin
b=new();
d=b;
d.print();
end

endmodule


code-2


class base;
task print();
........
endtask
endclass
class derived extends base;
task print();
........
endtask
endclass
module main();
base b; //Instance
derived d; //Instance
initial
begin
b=new();
d=new();
d.print();
end

endmodule


plz explain the meaning of declaration in this manner


Regards
Sunil.
 
Last edited:

You need to Understand the difference between virtual and non-virtual methods in SystemVerlog. Search for examples of that.
 

in code1 print() task of base class will run or execute ..............in code2 print() task of class derived will execute.......you can refer to www.testbench.in and refer to inheritance section of oops
 

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