The output KVL applies to -Vcc, Vce(Q2), Vce(Q1), + Vcc. We have:
-Vcc+Vce(Q2)+VC(Q1) = Vcc that is:
Vce(Q1)+Vce(Q2) = 2Vcc
if Vout = 0 we have (set Vout=0 and apply KVL to both lower and upper transistors):
-Vcc+Vce(Q2) = 0 ==> Vce(Q2) = Vcc
and Vce(Q1) = Vcc
This condition can be reached when Vs=0 if the npn and pnp behave exactly the same (as already said by FvM). Under this condition, if Vs <> 0 then
Vce(Q1) <> Vce(Q2) and of course Vce(Q1)+Vce(Q2) = 2Vcc applies.
This means the output voltage can span from -Vcc+Vce(Q2sat) to +Vcc-Vce(Q1sat)