# Class ab amplifier dc biasing

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#### paulmdrdo

##### Full Member level 3
Hi can you tell me what KVL loop in the circuit should I use to prove that VCE1 = VCE2 = VCC voltage. Thanks.

#### FvM

##### Super Moderator
Staff member
Obviously, the statement is not true, except for Vout = 0. Then the answer is trivial.

#### paulmdrdo

##### Full Member level 3
Obviously, the statement is not true, except for Vout = 0. Then the answer is trivial.
I forgot to mention that Vs is ignored. Can you tell me that trivial answer? Do we just say that it's equal VCC becuase it's labled VCC?

#### FvM

##### Super Moderator
Staff member
Vs = 0 doesn't strictly cause Vout = 0. R1, R2, Q1, Q2 can have different parameters.

You should know if labels "+VCC" and "-VCC" implicate voltage levels of +/- VCC, I just guessed so. But if you ask me if it's true...

To make it clear in circuit analysis terms, you would sketch voltage sources. Seriously, I don't understand what's exactly the objective of your question if it involves simplifications and inaccuracies.

#### Easy peasy

for that to be true the xtors must be very close in gain ...

#### paulmdrdo

##### Full Member level 3
for that to be true the xtors must be very close in gain ...

Hi. How is the voltage affected by the gain of the transistors?

#### albbg

The output KVL applies to -Vcc, Vce(Q2), Vce(Q1), + Vcc. We have:

-Vcc+Vce(Q2)+VC(Q1) = Vcc that is:
Vce(Q1)+Vce(Q2) = 2Vcc

if Vout = 0 we have (set Vout=0 and apply KVL to both lower and upper transistors):

-Vcc+Vce(Q2) = 0 ==> Vce(Q2) = Vcc
and Vce(Q1) = Vcc

This condition can be reached when Vs=0 if the npn and pnp behave exactly the same (as already said by FvM). Under this condition, if Vs <> 0 then
Vce(Q1) <> Vce(Q2) and of course Vce(Q1)+Vce(Q2) = 2Vcc applies.

This means the output voltage can span from -Vcc+Vce(Q2sat) to +Vcc-Vce(Q1sat)

paulmdrdo

### paulmdrdo

Points: 2

#### paulmdrdo

##### Full Member level 3
The output KVL applies to -Vcc, Vce(Q2), Vce(Q1), + Vcc. We have:

-Vcc+Vce(Q2)+VC(Q1) = Vcc that is:
Vce(Q1)+Vce(Q2) = 2Vcc

if Vout = 0 we have (set Vout=0 and apply KVL to both lower and upper transistors):

-Vcc+Vce(Q2) = 0 ==> Vce(Q2) = Vcc
and Vce(Q1) = Vcc

This condition can be reached when Vs=0 if the npn and pnp behave exactly the same (as already said by FvM). Under this condition, if Vs <> 0 then
Vce(Q1) <> Vce(Q2) and of course Vce(Q1)+Vce(Q2) = 2Vcc applies.

This means the output voltage can span from -Vcc+Vce(Q2sat) to +Vcc-Vce(Q1sat)

Hi. albg, thank you! This is the answer i was looking for!

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