Clarification on LDMOS VSWR power

[mtwieg]

Recently I've been reading up on LDMOS ruggedness and came across documentation claiming that they can deliver their full rated output power into high VSWR (like 10:1 and over). Is this just referring to the incident power on the load, or the net power into the load (that is, the difference between incident and reflected power)? It can't possibly be the latter case, right? As I understand it, if your VSWR is 10:1 then you have to dissipate ten times the power to deliver the same net power to the load than you would if VSWR was 1:1.

 

[WimRFP]

You are right, it is based on the situation where the LDMOS input drive equals the nominal drive to get the rated output power. It does say nothing about the actual output power (Pinc-Prefl). It just survives VSWR=10 (when max Tj is not exceeded) when it was delivering its rated power before the fault sitaution occured.

As the transistor may go into voltage and/or current saturation, the actual output power may deviate significantly from the power expected based on calculus for linear systems. Very likely you will get less then 33% of the output power at VSWR=1 (assuming (near) conjugate match operation).

If you would use the transistor in a class E design (that means operating below maximum gain for a given output power), the situation becomes completely different (it will very likely not survive).