Clarification on DRC errors

[Maithreyi]

Hi,
Iam doing a layout on Low Noise Ampifier in 0.13um technology using Assura Layout XL. I have encountered with DRC errors such as

1. Minimum DIFFUSION Density over 500x500 um^2 is 20%
2. Minimum PO1 density over 1000x1000 um^2 is 15%.

Can anyone please give me a solution to solve these errors.
And also, I want to know the reason, why do we need to maintain particular percentage of minimum DIFFUSION or PO1 density?

Thanks in advance

 

[manimail2007]

Hope you knwo DRC means Design Rule Checker.For each and every technology (here yours is 0.13um)file has its own design rules.in that design rule they predefined the size of lengths,widths,diffusion density,minimum gap has to be left for routing etc.,So we stick to those rules in order to design the chip in particular technology more over this would be followed in foundary also while manufacturing.

 

[erikl]

Can anyone please give me a solution to solve these errors.

Introduce dummy polygons. This will usually be done automatically during mask data preparation.

I want to know the reason, why do we need to maintain particular percentage of minimum DIFFUSION or PO1 density?

This is necessary for an effectively working CMP (Chemical-Mechanical Polishing) process, which is used to achieve good planarity after creation of the next layer. See this MOSIS document, item #4.

 

[afp2008]

Hi Maithreyi.

I also had these errors with UMC 130nm RF technology. I am also facing problems with assura LVS run: Did you have these errors in your design? Thanks for your attention.

 

[nature0303]

Yes,Each technology has it's range to ensure yield rate.