Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

clarification on basic not gate

Status
Not open for further replies.

Bhuvanesh Nick

Member level 1
Member level 1
Joined
Aug 22, 2013
Messages
33
Helped
1
Reputation
2
Reaction score
1
Trophy points
8
Visit site
Activity points
201
Screenshot (20).png

i am new to electronics

in above not gate circuit diagram how i am getting hight output for no input and no output for high input


doubt(even if its hight input..i have collector voltage am i right)
 

when input is zero, your transistor is off. there will be no current flow between collector and emitter. so CE junction acts as open, so full voltage appears across CE junction and you get output as high!
when input is high, the CE junction acts as short, so it appears as output is connected to ground. so output voltage will be 0.
 
I am assuming you want to use an input voltage between 0V and 5V? If so, you will never turn on the PNP the way you have drawn it. The base of a PNP needs to be more negative than the emitter to turn it on. You could use a PNP with the emitter to +5V and the resistor load to 0V.

Keith
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top