If the two clocks are XOR'ed, look for the XOR'ed output 1's posedge to coincide with a clock's posedge and negedge. The other clock is lagging this one.
Design a FF, Give one clock to the CLK input of FF, another clock to D input of FF
Look for the output of FF. If you get the '1' at the first clock, the clock at the D input is leading, else it is lagging.
Use a flip-flop, one is the data and the other is the clock.
Then to check the output of flip-flop, you will get the different result.
If the result is '1', it means the data is the leading one.
Or else the clock is the leading one.