Google finds for "sram array design" a lot of stuff, including PDF file which I won't link here because of bad forum rules, sorry.
You can do it yourself though.
That's true. But in many cases, input and output names were not shown clearly in these PDF files. For instance, my main question is that which signals are as the inputs of MUX used in SRAM array?
Thanks again
Google finds for "sram array design" a lot of stuff, including PDF file which I won't link here because of bad forum rules, sorry.
You can do it yourself though.
For data IO only you don't need a MUX, just a switch-over signal from input to output and vice versa.
For row- and column decoding see the standard peripheral circuits' descriptions for any RAMs, e.g. the following one for SRAM address decoders: View attachment 115839
Thanks. But suppose having a 32*32 SRAM array. If each column delivers one bit to output, array must have a MUX to select one output data associated with that selected cell. Is it true?