circuit schematic of an SRAM Array

[electronics20]

Hi
I need a circuit schematic of an SRAM array. I did not find anything on the internet!
Thanks

 

[tilz0R]

Google finds for "sram array design" a lot of stuff, including PDF file which I won't link here because of bad forum rules, sorry.
You can do it yourself though.

 

[electronics20]

That's true. But in many cases, input and output names were not shown clearly in these PDF files. For instance, my main question is that which signals are as the inputs of MUX used in SRAM array?
Thanks again

 

[erikl]

... my main question is that which signals are as the inputs of MUX used in SRAM array?

Which MUX do you think of? MUX for address/data IO ?

 

[BradtheRad]

Google finds for "sram array design" a lot of stuff, including PDF file which I won't link here because of bad forum rules, sorry.
You can do it yourself though.

Forum policy prefers we create Edaboard attachments if we are posting our own images, schematics, pdf's, projects, etc.

It is okay to give links to material at websites, if it is publicly available, and if we can expect the links to remain valid.

These policies have a certain amount of leeway, for individual cases which arise.

 

[electronics20]

Which MUX do you think of? MUX for address/data IO ?

MUX for data IO.
Thanks

 

[erikl]

MUX for data IO.

For data IO only you don't need a MUX, just a switch-over signal from input to output and vice versa.

For row- and column decoding see the standard peripheral circuits' descriptions for any RAMs, e.g. the following one for SRAM address decoders: View attachment Performance_Evaluation_of_6T_Sram_Cell_Structure_and_Peripheral_Circuitry.pdf

 

[electronics20]

For data IO only you don't need a MUX, just a switch-over signal from input to output and vice versa.

For row- and column decoding see the standard peripheral circuits' descriptions for any RAMs, e.g. the following one for SRAM address decoders: View attachment 115839

Thanks. But suppose having a 32*32 SRAM array. If each column delivers one bit to output, array must have a MUX to select one output data associated with that selected cell. Is it true?

 

[erikl]

It doesn't matter if you call it decoder or MUX, it's just the same. For different architectures, s. pp. 2 & 3 of the above overview paper.

 

[electronics20]

Does each column of an SRAM array need one sense amplifier? i.e 8 columns need 8 sense amplifier circuitry?
Thanks

 

[erikl]

Does each column of an SRAM array need one sense amplifier? i.e 8 columns need 8 sense amplifier circuitry?

The answer is on page 3 of the , paragraph Sense Amplifier:

number of sense amplifier is equal to number of columns ...

Those who are able to read
Are at an advantage, indeed.