CIC filter, 1-bit input bitstream, bad digital 15-bit output range

[golemek]

Hello,
I am designing the CIC filter to decimate the 1-bit output bitstream from sigma-delta modulator.

Here is a CIC spec:
CIC input resolution: 1-bit bitstream
CIC output resolution: 15-bit
Number of sections: N=4
Decimation factor: D=16

I have designed the CIC filter in VHDL.

I calculated that CIC Bmax= bin + Nlog2D + 1(sign)= 1 + 4*4 +1= 18 bit.

First, I converted the 1-bit stream from sigma-delta modulator to the 2's complement representation in my VHDL design:
'1' ----- "0000000000000000000001" (+1)
'0' ----- "1111111111111111111111" (-1)

After the simulation I am a little bit confused about CIC output range.

If I put to the CIC input log. '1', then I expected at CIC output the 15-bit value around 16383 ("011111111111111". But I get number 8192 ("010000000000000").

If I put to the CIC input log. '0', then I expected at CIC output the 15-bit value around -16384 ("100000000000000"). But I get number -8192 ("110000000000000").

FIR polyphase filter (15bit input, 15bit output) will be another stage connected to CIC filter.

Please help me, thank you in advance.

golemek

 

[steadymind]

hi,

i am also trying to design a decimation filter, but from what i can see is that "if u perform 2's complement on your output then u will get the expected code".

can u point to references for designing these filters?

 

[itmr]

hi
in now days i need to create some filter that remind your filter
did you use matlab to design it?
how did you design the cic filter? with cic compensation?