You need to ask yourself a couple of questions first:
1. What is my decimation factor? Which you've stated as 1024.
2. You are looking at a CIC filter, so how far down does your first side lobe need to be? This will set the number of stages of the CIC filter.
3. Now you know you're number of stages, is your bandwidth small enough compared to your sample clock frequency, such that your wanted signal isn't being distorted by multiple stages?
4. You can also determine the number of registers and adders, plus the size of each register and adder for your determined number of stages, such that you can determine an area estimate. You can also parallel up some of the Comb and/or integrators to reduce size, but at the cost of increasing clock frequency thus power consumption.