Sunayana Chakradhar
Member level 5
Hello,
I am somewhat experienced with vivado design flow. I have to design a packet processor on my Zynq 7020 FPGA. It has fragmentation, framing, parsing etc blocks in it. Is it better to use simulink for Zynq package or is it better to design it in VHDL on vivado? One of my colleagues told that "it might be better and easy to design in simulink so that on simulink the work can be divided between the OS/firmware side and hardware/FPGA side using simulink". I don't understand what is meant by this statement. Can someone clarify this.
I am somewhat experienced with vivado design flow. I have to design a packet processor on my Zynq 7020 FPGA. It has fragmentation, framing, parsing etc blocks in it. Is it better to use simulink for Zynq package or is it better to design it in VHDL on vivado? One of my colleagues told that "it might be better and easy to design in simulink so that on simulink the work can be divided between the OS/firmware side and hardware/FPGA side using simulink". I don't understand what is meant by this statement. Can someone clarify this.