chipscope : instances missing in hierarchy

[arthurbabloo]

chipscope hierarchy

hi,

i m using chipcsope pro 10.1 for the signal analysis,though i have successfully monitored quite a few signals in the design,
BUT when i insert the chip scope core using "chipscope pro core inserter" at the "modify connections" stage i m facing following problems

1- I do not find some signal that are present in design

2- Few source instances are missing in chipscope hierarchy (they are FSM's not any hardware components on FPGA)



can any one suggest the reason for this also how can i find thes instances in the chipscope hierarchy.



regards

arthur

 

[Tan]

missing +signals in chipscope

hi,

i m using chipcsope pro 10.1 for the signal analysis,though i have successfully monitored quite a few signals in the design,
BUT when i insert the chip scope core using "chipscope pro core inserter" at the "modify connections" stage i m facing following problems

1- I do not find some signal that are present in design

2- Few source instances are missing in chipscope hierarchy (they are FSM's not any hardware components on FPGA)



can any one suggest the reason for this also how can i find thes instances in the chipscope hierarchy.



regards

arthur

Hi arthur,
I too faced the same problem earlier.According to my analysis,when the mentioned signals are not used properly or when there is no change in the value of the signal then this condition happends.
Please analyse the signal you will know it.Or do one thing try to declare that signal in a port and see it in chipscope.

 

[arthurbabloo]

keep signal and view in chipscope

tan,

thanks for the reply,
adding signal in port list works
but wat about my 2nd question, do u hav an idea
why cant i see the instantiated modules in the chipscope hierarchy

regard
arthur

 

[Tan]

chipscope missing signals

tan,

thanks for the reply,
adding signal in port list works
but wat about my 2nd question, do u hav an idea
why cant i see the instantiated modules in the chipscope hierarchy

regard
arthur

Hi arthur,

I think the instantiated signal does not change its value all over the program.

 

[arthurbabloo]

signals not in chipscope

hi Tan,

i m not talking about the instantiated signals,
but the instantiated MODULES.
These modules are FSMs (state machines) and i know for sure that its out put control signal are changing(bcoz my code is working fine), but i dont see my modules in the CHIPSCOPE Hierarcy at the "modify connections" stage

really need a help 4 this one

 

[arthurbabloo]

chipscope inserter -edit

any one???

 

[arthurbabloo]

chipscope finding signals

well i have found a way to see the signals in chipscope

use
KEEP constraint as
(* KEEP = "TRUE" *) wire dout_test;
this will keep those signal after sythesis optimizaton that were removed by the optimazation process