Chipscope i/o set/reset

HI ALL

For those who used VIO core using chipscope i have some questions--

1- i running VIO using the old fashion way - generate ILA,ICON,AND VIO and connect them - there is any new way to do so from the .cdc file creating?

2 - i can toggle FPGA I/O directly or i can toggle just internal signals?

async_in / SYNC_IN - what it use for? what the core knows to d with it? what can i do with it?


i will be very happy to get good example or tutorial ( not like those who i can google?

Itamar

itmr said:

1- i running VIO using the old fashion way - generate ILA,ICON,AND VIO and connect them - there is any new way to do so from the .cdc file creating?

Click to expand...

As far as I know this is the only way to do it. Don't know about ISE 14.2 and Vivado 2012.2 I haven't used CS for those versions.
To connect a VIO with outputs you need to modify the RTL to drive signals in your design. I've had mixed results with trying to keep unconnected nodes in a design from being removed by synthesis. Some of the synthesis attributes have proven to be buggy.

itmr said:

2 - i can toggle FPGA I/O directly or i can toggle just internal signals?

Click to expand...

You could connect a VIO output to an FPGA I/O if you wanted to. There's no reason you can't drive any internal or I/O pin using it as the VIO core is instantiated in the RTL.

itmr said:

async_in / SYNC_IN - what it use for? what the core knows to d with it? what can i do with it?

Click to expand...

It's used to capture inputs into the VIO to be read by the CS software. You can connect to either asynchronous or synchronous signals.

itmr said:

i will be very happy to get good example or tutorial ( not like those who i can google?

Click to expand...

Have you tried Xilinx's website? Probably not, as the CS documentation explains all of the above.

Regards,
-alan

You could check these: https://www.youtube.com/results?search_query=xilinx+chipscope