Chip corner stress in IO ring assembly

Status
Not open for further replies.

analog_ip

Newbie
Joined
Oct 10, 2012
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Bangalore
Activity points
1,305
Hi I am working on IO corner cells.

Can anybody explore about corner stress in IO ring.

Thanks
 

You would need to check with the design rules, normally at chip corner there is a keep out area, 0.18 tsmc is 50u for example.
Metals at the corner edge normally go edge to edge using a 45 degree path.
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…