checki ng of verilog netlist before Place & Route

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viswanadh_babu

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Hai all,

What are the various checks that are to be perfomed on prelayout verilog netlist by physical design engineer , before implementing P& R .

Regards,
KVB
 

1) No inputs should be floated.
2) There should not any assign statements.
3) All floating input connected to tie cells.
4) Adding Spare cells ( It depends on methodology, some guys will put in the P&R)
5) proper naming rules for the netlist etc....

Thanks,
Chaitanya.
 

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