characterisation of standard cell library

[sudheerprasad]

standard cell library characterization

hi,
iam presently studying about characterisation of cell library.i down loaded a .13u library from www.vlsitechnology.org .A sample is given below
//power characterisation for an input pin of AND gate
power_lut_template(pwr_x2_676_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 5.2, 20.8, 62.4, 156.0, 322.4" ) ; }

internal_power(i1_q_p) { /* a2_x2 32.64 nW/MHz */
related_pin : "i1" ;
power(pwr_x2_676_5x10) {
values( " 16.32, 16.51, 16.62, 16.62, 16.54", \
" 16.04, 16.21, 16.35, 16.36, 16.29", \
" 15.99, 16.14, 16.29, 16.32, 16.25", \
" 16.05, 16.16, 16.32, 16.36, 16.30", \
" 16.39, 16.42, 16.56, 16.62, 16.56", \
" 17.16, 17.07, 17.15, 17.22, 17.18", \
" 18.62, 18.36, 18.35, 18.39, 18.36", \
" 21.10, 20.63, 20.47, 20.46, 20.42", \
" 25.22, 24.48, 24.10, 23.99, 23.92", \
" 31.87, 30.76, 30.08, 29.79, 29.67" ); }}

how do we produce the above LUT
the units of power is pico watt

differnce between internal_ pwr 32nw/Mhz and pwr values in the lut
can u briefly explain how to generate these values using eldo ,hspice or cadence.

 

[tomorrowglue]

standard cell library characterisation

The left top data represent when "input_transition_time" = 20 and "total_output_net_capacitance"=5.2. This is a 2-dimensional table, so "input_transition_time" is the vertical index, and "total_output_net_capacitance" is the horizontal index.

To generate the data in circuit simulation (spice etc.):
1) input connect to a voltage supply, which gives a rise/fall step, and with transition time = "input_transition_time". Note: the "input_transition_time" usually refer to from x% to y% of the step (20%-80% for exampel), this can be found in the same file "slew_upper_threshold_pct_rise".
2) output connect to a capacitance = "total_output_net_capacitance". The other side of the cap connects to ground.

There are several tools that can generate the library files, like Cadenc ELC, NanGate. What they do is just automate the spice simulation and the process to collect data.