Changing clock inverter buffer at the init stage

[kannanunni]

I need to change the clock inverters at init stage to a compatible inverter(ie, ports should be matched).
how??

this is because as per convention no clock buffers should be there in any critical path at init stage..
it should be present only after CTS ..


how could i do this??

one of r2r path look like this..


Path 1: VIOLATED Setup Check with Pin EXECUTE_INST/\p_reg[31] /state_remap/DFF/
CK
Endpoint: EXECUTE_INST/\p_reg[31] /state_remap/DFF/D (^) checked with
leading edge of 'm_tdsp_clk'
Beginpoint: EXECUTE_INST/\sel_op_b_reg[2] /state_remap/DFF/Q (^) triggered by
leading edge of 'm_tdsp_clk'
Path Groups: {reg2reg}
Other End Arrival Time 1.000
- Setup 0.268
+ Phase Shift 3.300
+ Cycle Adjustment 6.600
- Uncertainty 0.200
= Required Time 10.432
- Arrival Time 11.532
= Slack Time -1.100
Clock Rise Edge 0.000
+ Network Insertion Delay 1.000
= Beginpoint Arrival Time 1.000
Timing Path:
+-----------------------------------------------------------------------------------------------------------------------+
| Instance | Arc | Cell | Slew | Delay | Arrival | Required |
| | | | | | Time | Time |
|---------------------------------------------------+---------------+--------------+-------+-------+---------+----------|
| | clk ^ | | 0.000 | | 1.000 | -0.100 |
| EXECUTE_INST/RC_CG_HIER_INST25/RC_CGIC_INST/LATCH | CK ^ -> ECK ^ | TLATNTSCAX16 | 0.000 | 0.000 | 1.000 | -0.100 |
| EXECUTE_INST/\sel_op_b_reg[2] /state_remap/DFF | CK ^ -> Q ^ | SDFFRX4 | 0.049 | 0.297 | 1.297 | 0.196 |
| TDSP_CORE_GLUE_INST/g8116 | A ^ -> Y ^ | AND2X1 | 0.042 | 0.125 | 1.421 | 0.321 |
| TDSP_CORE_GLUE_INST/g8212 | AN ^ -> Y ^ | NOR2BX2 | 1.362 | 0.773 | 2.194 | 1.094 |
| TDSP_CORE_GLUE_INST/g8454 | A1 ^ -> Y ^ | AO22X4 | 0.057 | 0.613 | 2.808 | 1.707 |
| TDSP_CORE_GLUE_INST/g8331 | C0 ^ -> Y v | AOI211X4 | 0.079 | 0.034 | 2.842 | 1.741 |
| TDSP_CORE_GLUE_INST/g8330 | A v -> Y ^ | INVXL | 0.705 | 0.377 | 3.219 | 2.118 |
| MPY_32_INST/g1676 | B ^ -> Y ^ | AND2X1 | 0.037 | 0.341 | 3.559 | 2.459 |
| MPY_32_INST/g1792 | A ^ -> Y v | XOR2X4 | 0.130 | 0.242 | 3.801 | 2.701 |
| MPY_32_INST/M16X16_INST/mul_8_14/g27586 | A v -> Y ^ | CLKINVX8 | 0.055 | 0.061 | 3.862 | 2.762 |
| MPY_32_INST/M16X16_INST/mul_8_14/g28678 | A1 ^ -> Y ^ | OA22X4 | 0.108 | 0.201 | 4.063 | 2.963 |
| MPY_32_INST/M16X16_INST/mul_8_14/g28655 | C0 ^ -> Y v | OAI221X4 | 0.292 | 0.203 | 4.266 | 3.166 |
| MPY_32_INST/M16X16_INST/mul_8_14/g28598 | B1 v -> Y v | OA22X4 | 0.056 | 0.222 | 4.488 | 3.388 |
| MPY_32_INST/M16X16_INST/mul_8_14/g28410 | S0 v -> Y v | CLKMX2X12 | 0.089 | 0.267 | 4.755 | 3.655 |
| MPY_32_INST/M16X16_INST/mul_8_14/g26363 | B v -> Y v | OR2X1 | 0.046 | 0.121 | 4.877 | 3.777 |
| MPY_32_INST/M16X16_INST/mul_8_14/g27902 | AN v -> Y v | NOR2BX4 | 0.043 | 0.117 | 4.993 | 3.893 |
| MPY_32_INST/M16X16_INST/mul_8_14/g28301 | S0 v -> Y ^ | CLKMX2X12 | 0.099 | 0.299 | 5.293 | 4.193 |






it includes CLKINVX8 and so on...
how could i remove this??

 

[sharath666]

The question is not very clear. Do you mean to say you need to change the instance of the invertor so that you get better delay characteristics?

 

[kannanunni]

The question is not very clear. Do you mean to say you need to change the instance of the invertor so that you get better delay characteristics?

yes..
i need to get better delay characterstics..