dick_freebird
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Yes, ceramic capacitors may become easily short circuited.
I have bought a new transistor and followed the mentioned biasing sequence. This time ok no short at the drain side. However, when I measured IDS, i got it 0.1 mA suppose to be 13 mA according to the biasing point. Therefore, if there is no current at the drain side means I can get the expected results like S21. So, what is the thing that make the current not to flow to the drain side? How about bypass capacitor for being not selected properly? could cause this problem?
Yes I have followed biasing sequence by apply pinch off gate voltage -5V first then drain voltage 28 V. Then i rump up the gate voltage to -3.2 V according to biasing point in simulatation. At this point, suppose to get 13 mA drain current. However, the current was very small 0.1 mA. If i rump up the gate voltage more towrds -3 V. I can see the drain voltage going up from 28 V to 40 V. The changing of drain voltage what does it mean? As firstly i have fixed it to 28 V.The gate voltage required for your desired bias point may not be exactly the same as that printed on the datasheet. As an example, if you apply say, exactly -2.4 V to the gate, hoping to get an IDS of 100 mA and you see an IDS of 50 mA or 200 mA, it's because the bias point is slightly different for every device and it's not a major problem either... just one of those things.
Although the process for fabricating a run of GaN wafers is very well-controlled, some batches of devices or even devices within a batch will behave differently to one another. This is called "process variation" and it's a lot more difficult to design with when you don't have the ability to control the bias voltage off-chip, as you do. The drain current also changes over temperature too, even when the gate voltage doesn't change.
It shouldn't be a problem if you need to use -2.7 V or -2.3 V to get the right bias point. Just remember to apply -10 V (or something in that region) to the gate before you apply the drain voltage, then ramp up the gate voltage slowly until the drain current is the value you want. I once blew up a prototype device because I flicked the wrong switch on a dual power supply by mistake. It was a very expensive mistake!
So your amplifier is oscillating and it disturbs the power supply.While you're sliding Vgs, Ids should increase accordingly.There shouldn't be any step-up or sharp changing.
I have simulated stability using k delta test and was uncondition stable k>1 & delta <1. Any other way to verify stability?
Can the decoupling or bypass capacitor cause this instability in the power supply?
Regarding the decoupling caps, I have only used one cap of 10 pF for each side (drain and gate).
"It's probably best to use the recommended datasheet capacitors" Use same caps Even if my design biasing point is slight different from datasheet PA design biasing point. For them, VDS= 28 V, VGS = -2.7 V
Of course ! If a high ESR capacitor is used, \[ V_{cc} \] supply line will act as high impedance rather than short circuit for AC and this will return to oscillating.
Sure.. Decoupling capacitors especially ceramic types can easily be short circuited. Electrolytic caps. may also cause..
Thank you for your suggestions, by adding more caps i could stabilize the dc power supply. And i can see current at drain side. My question now. But still the response s-parameter is not what i was expecting. It looks like there was shifting to low freq below 2 GHz. Target band 3.4-3.6 GHz. So, Is s2p file of those caps can show me the effect of caps in the simulation? As some of caps i could not get their RLC model circuit?
Black screw for ground connection. The patch under screw is ground.
Does this variation affect the results (S-parameters)? As in the simulation, i applied -3.2 V to get 13 mA IDS which is the required bias point, but during the measurements, I could not get this amount of current with the same gate voltage applied. I only could get IDS of 13 mA with VGS = -2.9 v which is different from that in the simulation VGS = -3.2 V. As a result, the s-parameter response (S11 & S22) was shifted from 3.5 GHz to 1.5 GHz when comparing simulation with measurements.The gate voltage required for your desired bias point may not be exactly the same as that printed on the datasheet. As an example, if you apply say, exactly -2.4 V to the gate, hoping to get an IDS of 100 mA and you see an IDS of 50 mA or 200 mA, it's because the bias point is slightly different for every device and it's not a major problem either... just one of those things.
Although the process for fabricating a run of GaN wafers is very well-controlled, some batches of devices or even devices within a batch will behave differently to one another. This is called "process variation" and it's a lot more difficult to design with when you don't have the ability to control the bias voltage off-chip, as you do. The drain current also changes over temperature too, even when the gate voltage doesn't change.
It shouldn't be a problem if you need to use -2.7 V or -2.3 V to get the right bias point. Just remember to apply -10 V (or something in that region) to the gate before you apply the drain voltage, then ramp up the gate voltage slowly until the drain current is the value you want. I once blew up a prototype device because I flicked the wrong switch on a dual power supply by mistake. It was a very expensive mistake!