cells with multiple threshold voltage in design compiler

[mehran1367]

hi all,
how can we have cells with 2 different threshold voltage in a module?.(im using design compiler)


actually i want to use cells with more threshold voltage in paths with more slack , and i want to use cells with lower threshold voltage in paths with lower slack.( i want to decrease leakage power consumption).

plz helppp.

 

[oratie]

Add two (or more) libraries with different voltage threshold cells in target_library and switch on leakage optimization (set_leakage_optimization true). Then, compile your design.

 

[YuLongHuang]

Just as "oratie" said, what you need to do are
1. setup the target/link library such that the tool can apply it.
2. constrain the design such that the tool know whether to apply it.

For more detail about (2), for example, if bottleneck of your design is power,
during the optimization, the tool will apply high-Vt cell to improve the leakage power.
While the bottleneck of your design is timing performance, the tool will some low-Vt cell to improve the timing until it met.

 

[mehran1367]

you r right but i dont know how to change libraries. is there any manual?

 

[oratie]

You do not need to change libraries manually. Just enlist all available multi-Vt libraries in one variable target_library. Then, specify to DC, what is your primary goal (timing or power or area or ...). The tool will automatically select appropriate cells from different libraries per each path (in one path it will use High-Vt cells, in another - Low-Vt cells ...)