CDC-Write clock slower than read clock in Video application

[adivy]

I have to read 14 bits of data from clk domain A(7MHz) and write it to a clk domain B(21Mhz).
I'm dealing with video data from camera as the 14 bits as input.
Image resolution is 384x288 and frame rate 50fps.
Output and input frame rates are the same only the clock rates are different.
How do I go about solving this CDC bottleneck using a FIFO?How do I calculate the depth of the FIFO?

 

[ads-ee]

1. Is the 14-bit data on domain A serial or parallel?
2. Is clock domain B (21 MHz) derived from domain A (7 MHz) using a PLL/MMCM/etc.?

Depending on the answer to these two questions the design can be simplified in various ways and will not require a FIFO.

If you are set on using a FIFO. If the data is parallel 14-bit on domain A then write it to a CDC FIFO using domain A clock. Wait for empty to be unasserted and read the 14-bit data from the FIFO using domain B clock.
The depth of the FIFO only needs to be 1 data word, unless there is some further specification that requires you be able to clock out bursts of data on domain B.

Regards

 

[adivy]

Hi ads-ee,

Thanks for your reply.
The 14-bit data on domain A is parallel and
clock domain B is not derived from domain A.

I have to take the camera input and send it out on the camera link.
So video input from the camera is Domain A and the camera link output is Domain B.

Do I have to use FIFO plus double buffering?I don't understand how can I send a continuous video out from the camera link .

 

[TrickyDicky]

Are you sure the output resultion is the same as the input? With the same frame rates and same resultion you expect the same clock speed, unless the data bus size is different? what are the data formats for input and output? Or are you expecting to only enable every 1/3 pixels?

You will need a fifo but this will take care of all buffering. If the resolutions are different you will need some form of scan conversion, which may involve a frame buffer.

 

[ads-ee]

Tricky,

The OP is taking data at a lower clock frequency 7 MHz and sending over an interface at 21 MHz 3x the data rate.

adivy,

Yes a FIFO is probably the simplest solution (you don't need to double buffer), though it could be done using double buffered registers and a signal that lets the 21 MHz domain know that data has updated. If you aren't running short of memory or need to reduce power consumption (RAMs eat more power) then use the FIFO and save yourself some headaches.

To send continuous 7 MHz video out the 21 MHz link you'll have to know the protocol of the 21 MHz link. If it's data on every clock you would probably have to do something like what Tricky suggests. Without details on the link protocol it's hard to say what you can or can not do with the transmission of the camera's 7 MHz video over it.

Regards