cc2500 Rf transciver interfacing with Spartan 3 Fpga

[afzaalabbasi]

i want to interface cc2500 wirless module directly with fpga i have included the registers configration files(.h files) exported from Smart RF Studio in verilog now further i am stuck soo please i need your help.....

 

[ads_ee]

Correct me if I'm wrong, but it seems to me that you've taken a C code driver for the cc2500 module and converted it to Verilog?

Well you need to create a hardware design that interfaces to the transceiver over whatever it's control interface is and then use that design to "talk" to the transceiver with some control logic that uses the .h file you converted to write those values into the transceiver device.

Regards,
-alan

 

[cwjcwjcwj]

I guess the first thing you need to understand is how to write a thread in a forum to explain your problem. Not just stuck and help pls.....

How do you expect people to understand this?

 

[afzaalabbasi]

i i want to configure registers of (Quasar UK ‘TRX1’ hybrid transceiver) module in verilog to use it as transceiver.i have included the header files in my verilog code.Now the next step is to load all registers values in the module in initial block in verilog. Fpga act as master and transceiver module act as slave..So can you tell how i can load all registers values and address..

 

[joelby]

You can't load all of the registers into an external peripheral in an initial block. Generally, you'll need something like a state machine that programs each register, one by one.

 

[afzaalabbasi]

i have to load many register values as per required to load the transceiver in transmitter mode or receiver mode how should i go for state machine approach when i have to send the values in the simple way that is just send the register address and then its value then how could i do this with the state machine if no state is changing what will i take state (reference) that will change and i will send the next address and value
i am confused on this...

 

[joelby]

You might want to read up on state machines to see how they're used on FPGAs.

In pseudo code,

State 1: (at power up) - wait some time for the CC2500 and other peripherals to finish powering up. Then go to state 2.
State 2: Send register address 1. Go to state 3.
State 3: Send register value 1. Go to state 4.
State 4: Delay (if necessary). Go to state 5.
State 5: Send register address 2. Go to state 6.
State 6: Send register value 2. Go to state 7.
..
State n. Signal that initialisation is complete. Remain in state n (i.e. do nothing)

 

[afzaalabbasi]

can anyone have small example of configuration of Any RF Module in verilog???