Case statement in Verilog

[hossam abdo]

Hello

addrs is 5 bits

case (addrs)
5'h10: statement; //case 1
5'h11: statement; //case 2
5'h12: statement; //case 3
5'h20: statement; //case 4
default: statement;
endcase

In cases(2,3), the MSB is dontcare, can I select only the first 4 bits withen the same case statement?

Thanks in advance.

 

[carbon_79]

Hello

addrs is 5 bits

case (addrs)
5'h10: statement; //case 1
5'h11: statement; //case 2
5'h12: statement; //case 3
5'h20: statement; //case 4
default: statement;
endcase

In cases(2,3), the MSB is dontcare, can I select only the first 4 bits withen the same case statement?

Thanks in advance.

It seems the definition a bit error . If it's a 5 bit addr, it cannot represent 5'h20 as it can only be 0 or 1 .
i guess the addr should be
5'b01000 //case 1 , 5'h08
5'b01001 //case 2 , 5'h09
5'b01010 //case 3 , 5'h0A
5'b10000 //case 4 , 5'h10

or 6 bit addr
6'b010000 //case 1 , 6'h10
6'b010001 //case 2 , 6'h11
6'b010010 //case 3 , 6'h12
6'b100000 //case 4 , 6'h20



Then actually you can use only 3 bit of the addr to check the case

assign case_addr = {addrs[4],addr[1],addr[0]};

case (addrs)
3'b000: statement; //case 1
3'b001: statement; //case 2
3'b010: statement; //case 3
3'b100: statement; //case 4
default: statement;
endcase