That's all. Keep current density constant.- Hi, would you go to the party on which is 10 liters of vodka?
- hmm, for how many people?
I told you, it might be hard. Above consideration were taken for "typical" corner. Fast transistors might be strangled by output stage biasing.Myself said:By biasing all FETs close to strong inversion (for speed and matching), lets say IC=5, and with reasonable channel length for example 0.5µm, the dimensions of these guys should be: 3.5µm/0.5µm for NFET per 10µA current and 10µm/0.5µm for PFET per 10µA. For different current, scale NF or M in respect to current ratio.
Such biased transistors might has ca 0.65V Vgs at room temp (NMOS) varied across temp range -40°C - 125°C between ≈0.53V and ≈0.83V.
Vdsat of above mosfets will be ca 200mV at room temp and varies between 160mV(-40°C) and 260mV(125°C).
So, for single cascode there is 125mV/mosfet of VDS margin (room temp) and 100mV (-40°C) or 150mV (125°C).
For double cascode, there is only 50mV of VDS margin for all 3 mosfets, so they should be biased then deeper in moderate inversion (i.e. IC=1 means all widths 5× higher for the same current, but 65mV lower Vdsat).
There are no big or small but optimal or not sizes.Junus2012 said:I reached PMOS W=240 µm for the upper transistors then 120 µm then 60 µm for the biasing class AB, all with L= 1µm and I think it is bnig values when I compare it to design from literature, right ?
Junus2012 said:althaugh I don't know about the expression equation for all the three vbias volategs in your scheme and in the same time feeling ashy to ask you for it
So, you have done something wrong. Input devices of such boosters should be complementary, were they?1. With single ended booster ampliifer I use VD1
2. With fully differerntial amplifier booster I used VCM (of the booster) = VB2 , not working with VD1
Pros: almost none (higher headroom for current sources, so double cascode is possible, blabla) - but again, we back to my first post - 140dB is really ridiculous gain which asking for troubles - none book (at least, I don't remember any) mention this - risk of negative resistance seen from supply. You can have everything fine in simulations, but in silicon opamp are ringing because of it.I would like to ask you please about the advantagues of including the level shifter scheme ?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?