#### vickyuet

##### Member level 2

Dear All,

I had written a verilog hdl code for carry lock ahead generator.The equations for generate,propagate,carry and sum are implemented through for loop using gate level as well as behavioral level.If anyone can tell that my code is professionally ok or any modification still required.

I had shown here only main part of full code.

//////////////////////////////////////////////////////////////////////////////////////////////////

c[0] =carry_in; //store input carry

for(i=0; i < data_width; i=i+1)

begin

gen

I had written a verilog hdl code for carry lock ahead generator.The equations for generate,propagate,carry and sum are implemented through for loop using gate level as well as behavioral level.If anyone can tell that my code is professionally ok or any modification still required.

I had shown here only main part of full code.

//////////////////////////////////////////////////////////////////////////////////////////////////

c[0] =carry_in; //store input carry

for(i=0; i < data_width; i=i+1)

begin

gen

*= reg_data1**®_data2**; // generate function*

propprop

*= reg_data1**^reg_data2**; // propogate function*

c[i+1] = genc[i+1] = gen

*|(prop**&c**) ; // carry function*

// sum function

sum_cla// sum function

sum_cla

*= prop**^c**;*

end

carry_out = c[data_width] ; //carry_out is taken from MSB of c(carry function)

/////////////////////////////////////////////////////////////////////////////////////////////////

I had modified to use behavioral level for above.

/////////////////////////////////////////////////////////////////////////////////////////////////

for(i=0; i < data_width; i=i+1)

begin

//generate function

if (reg_data1end

carry_out = c[data_width] ; //carry_out is taken from MSB of c(carry function)

/////////////////////////////////////////////////////////////////////////////////////////////////

I had modified to use behavioral level for above.

/////////////////////////////////////////////////////////////////////////////////////////////////

for(i=0; i < data_width; i=i+1)

begin

//generate function

if (reg_data1

*&& reg_data2**)*

gengen

*= 1'b1;*

else

genelse

gen

*= 1'b0;*

// propogate function

if (reg_data1// propogate function

if (reg_data1

*==reg_data2**)*

propprop

*=1'b0;*

else

propelse

prop

*=1'b1;*

c[i+1] = genc[i+1] = gen

*|(prop**&c**) ; // carry function*

// sum function

sum_cla// sum function

sum_cla

*= prop**^c**;*

end

carry_out = c[data_width] ; //MSB for

////////////////////////////////////////////////////////////////////////////////////////////////

The results of both are same.Can we modify c[i+1] = genend

carry_out = c[data_width] ; //MSB for

////////////////////////////////////////////////////////////////////////////////////////////////

The results of both are same.Can we modify c[i+1] = gen

*|(prop**&c**) ; using if/else or any other behavioral statements?*
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