Jetach
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Hello,
I need a way to implement a carry chain delay for a high resolution TDC.
I am only doing simulations in verilog, but I do not know how to create this time delay using verilog.
any help would be appreciated, I am attempting to implement this design here:
Also, my DFF will need to require two clock inputs, but would only one of them be the actual clock with another 180 degrees out of phase to act as a stop?
I need a way to implement a carry chain delay for a high resolution TDC.
I am only doing simulations in verilog, but I do not know how to create this time delay using verilog.
any help would be appreciated, I am attempting to implement this design here:
Also, my DFF will need to require two clock inputs, but would only one of them be the actual clock with another 180 degrees out of phase to act as a stop?
