Hi everyone, I am a newbie to the analog field and I have implemanted robert millikens capless LDO in 90nm technology,which has 3.3V input and 2.8V output for a load of 100pf(internal) with max load current of 50mA. I am getting line regulation of 31mV/V at 50mA(max) and 11mV/V at 0mA(min) and psrr is -35dB at 100Khz, accourding to my knowledge it is bad. how can i improve my line regulation and psrr. and all other parameters are turning out to be good ,say my open loop gain is 61.2dB ,load regulation is 0.33 V/A,settling time is 2us.
Please help me.
thanks