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Capacitor Mismatch Coefficient for gpdk 180nm technology

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Indrajit Das

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Hi experts,

I am designing a 8 bit CDAC for the SAR ADC that I want to design for my masters project. Regarding this, I want to know about mismatch coefficient of capacitors (Ac) for gpdk 180 nm tech. because, using the mismatch concept I can decide on the LSB cap value that I need to use.

Anyone having any information regarding this, please help me out....

Regards,
Indrajit
 

Hi erikl,

Thanx for the reply. But, can you please tell me, the data provided by you is of which foundary? And can I get the full document, ie the source file, I would like to have detailed understanding of the topic.

Indrajit
 

... can you please tell me, the data provided by you is of which foundary?
It's from Atmel.

And can I get the full document, ie the source file, I would like to have detailed understanding of the topic.
Sorry, no. It's company confidential, signed by an NDA. Hope for your understanding.

Anyway: it doesn't disclose more details for understanding the context. The published data are just the result from silicon extraction measurements on many wafer lots.
 

It's from Atmel.


Sorry, no. It's company confidential, signed by an NDA. Hope for your understanding.

Anyway: it doesn't disclose more details for understanding the context. The published data are just the result from silicon extraction measurements on many wafer lots.

Hi erikl,

Yes, I got ur point.

But, regarding this I would like to ask something. Actually my prof has asked me to show some kind of analysis of the capacitor mismatch that occurs in a real fab scenario in my interim progress report. For that, I am doing various kinds of research over the internet to get whatever possible information that I can get.

In the file that you earlier attached, there was a formula, MIM-cap-mismatch = 1.6% / sqrt(W*L) for 1sigma distribution or 4.8% / sqrt(W*L) for 3sigma
Now, upto which extent does this formula hold while talking about 180nm process? I understand that these figures are for atmel and will vary for a different fab. But, as per your knowledge, how much variation do you think will be there if I change to a different fab facility remaining at the same technology node? Actually what I am trying to know, is that if there is any general guideline or theoretical study regarding mismatch study of capacitors available, as I can refer that for my work.

Any information or input regarding this will be highly appreciated....

Regards,

Indrajit
 

Hi, Indrajit
Mismatch is from process control of fab, so it is different for different fabs.
By the way, different capacitors (MIM-cap, MOM-cap, MOS-cap, etc.) will have different mismatch performance. It is better for you to select one foundry to get the relative data.
 

... MIM-cap-mismatch = 1.6% / sqrt(W*L) for 1sigma distribution or 4.8% / sqrt(W*L) for 3sigma
Now, upto which extent does this formula hold while talking about 180nm process? I understand that these figures are for atmel and will vary for a different fab. But, as per your knowledge, how much variation do you think will be there if I change to a different fab facility remaining at the same technology node?

Hi Indrajit,

that's the only mismatch info I got for a 180nm process, sorry. As littlej_zju stated above, such values are the statistic result of an individual fab's process control (and their reproducibility!). To get such values, you'll have to be a customer of such a fab/foundry, and usually have to sign an NDA for not revealing their data. So it won't be easy to obtain such data from competitive processes resp. fabs. May be you can find comparison values in the literature, but most of (mis)match papers deal with MOSFET mismatch, much more than with MIMcaps.

Good luck!
erikl
 

Thanx erikl, littlej_zju....for the reply. Got the point. I understand the point that these statistical data varies from foundry to foundry. So, its difficult to have any kind of genralized theory out of it. May be I would find relevant papers in the literature.

Regards,

Indrajit
 

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