capacitor mismatch analysis

[nijMcnij]

capacitor array mismatch matlab

hello all,

i am doing the layout of the capacitor array used in an ADC, i would like to find out how much mismatch the layout will have....

i thought maybe monte carlo anlysis...but how?
many thanks

 

[bastos4321]

hello all,

i am doing the layout of the capacitor array used in an ADC, i would like to find out how much mismatch the layout will have....

i thought maybe monte carlo anlysis...but how?
many thanks

Make a model of the ADC in matlab and then is easy to include the mismatch of the capacitors.

Bastos

 

[oxide]

use the MC tool within spectre.

 

[nijMcnij]

yes, but how

 

[cretu]

yes, but how

If you are using Virtuoso from cadence you can do the following:
1.from the schematic open Tools-Analog environment
2. From the Analog environment window open Tools-Monte CArlo
3. You get a pop-up window where you can choos #of runs, analysis variation, param swept and signals to be shown

I hope this helps
rgds

PS you need to have statistical models

 

[hltong]

Here is a sample .
10Bit 100M ADC . MC cap mismatch is 0.3%

 

[nijMcnij]

hltong how did u calculate this figure for the mismatch...i mean what was the circuit configuration that u used during the MC analysis?

 

[yeziwong]

capacitor mismatch lead the gain error in each stage, thus you can use simulink in matlab and analysis how capacitor mismatch affects. regards

 

[invent]

Doesn't the maximum mismatch depend on the process itself?
Better process tend to have less process variation and less mismatch.

 

[cretu]

Doesn't the maximum mismatch depend on the process itself?
Better process tend to have less process variation and less mismatch.

Partially you are right. Better processes tend to have less absolute variation. However, mismatch is usually a different story and depends entirely on your layout. End of story 2 structures(Caps, resistors) can vary a lot due to the process(+/-30% even 50%), but relative to each other you can have less than1-2% variance