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capacitor and resistor layout question

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Robertt

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poly resistor layout

Should I put capacitors and resistor in Nwell?

Added after 11 minutes:

one more question:

I use poly to draw the resistor layout, if it is not good useing the minimum ploy width as the resistor width.

Say, is the minumum poly width should be 0.6um. I draw the resistor with 0.6um width and then adjust the length to get the desired resistance value. Is that good?

I doubt it. My reason is that, in process, there will be variations, if we use the minimum width, the resistance value variation should be large because of the process variation. So we should choose lager width.

But I am not sure if I am correct or my worry is redundant. If I am correct, which width value we should choose for resistor layout? in the above example, 1.2um is a good choice?
 

nwell resistor layout

I just don't get it, everybody seems to belive that techology should be kept a secret but the keep asking questions about sizes.
Anyway:
1) You put caps and resistors over (not "in") Nwell to decrease the noise injected to/from substrate. You know better if that is an issues in your circuit.
2) minimum value for a resistor is not the minimum value for poly. E.g., in a 0.25u process, minimum resistor width is 2u (as far as I remeber). The reason for that is terrible matching if you use less, and contacts at the end.
Now, the matching you need AND the techology should decide the width.
As for the value, you have to add interface resistance (contacts), not only poly.
 

vdd between resistor layout

Drawing resistor in layout is technically based on the number of R_sq.

Required sheet resistance R = R_sq x L/W, where W is the polysilicon width or the metal_1 width. In most cases, this is adjustable by you, not always the minimum width.

W and L in CAD tools is represented by the number of λ used.

If you are working in deep submicron, use minimum width to reduce the effective width for parasitic capacitance with respect to the bulk. In this case, your minimum width is 2λ = 2 x 0.6-µm = 1.2-µm in your design.
 

design resistor layout

when u draw the layout, u should be based on the design rule file. and simulation, u should make the corner analysis.
in the PCM file, the foundary give the offset of resistor.
 

poly and resistor nwell

Good job eleborating REs by skyhigh..that the way to calculate resistor,by the Rsq.

It's your issues to choose the resistor value and even the technology. One of it by using poly to get the high resistance but even short circuit trnsistor can give high resistor( for nFET,connecting the base to drain@Vdd).

If your layout uses many transistor, using poly as resistor is ok, but do consider the matching of the transistors and the poly resistance. If u use transistor the matching problem is less complicated.
 

resistor layout matching

it depends on what kind of resistor (poly,diff, well, ion inplant) or capacitor you use, and depend what type ( p or n)
 

high resistor poly minimum length

starcoming said:
it depends on what kind of resistor (poly,diff, well, ion inplant) or capacitor you use, and depend what type ( p or n)

I might add that also depends on kind of precision you are trying to get and the money you are allowed to spend on very well controlled ohms/square for a resistor. MAin stream technologies can't achieve better than 15-20% variations for the best resistor they can offer. To add to that mismatch/variation, all the resistors you can get will have some temperature dependent coefficients which can have a positive or negative behaviour
 

minimum width of poly 2 for resistor

ocarnu said:
1) You put caps and resistors over (not "in") Nwell to decrease the noise injected to/from substrate. You know better if that is an issues in your circuit.

I want to know what Nwell was connected to, one port of caps/res. or VDD? which is better?
and can it connect to GND?
thanks!
 

poly capasitor layout

aicder said:
ocarnu said:
1) You put caps and resistors over (not "in") Nwell to decrease the noise injected to/from substrate. You know better if that is an issues in your circuit.

I want to know what Nwell was connected to, one port of caps/res. or VDD? which is better?
and can it connect to GND?
thanks!


The nwell is of course connected to vdd
 

what do u means by capacitors and resistors

oversizing or undersizing that occurs during photolithography and poly etching can have a significant effect upon narrow poly resistors i.e. Narrow res will exhibit large process variations dueto linewidth control. This effect of linewidth variation can be min by increasing width of the res to several times minimum. Extremely narrow poly resistors may also experience increased res variability due to the growth of individual grains across the entire width of the res (bamboo effect).
 

better capacitor layout

gdhp said:
aicder said:
ocarnu said:
1) You put caps and resistors over (not "in") Nwell to decrease the noise injected to/from substrate. You know better if that is an issues in your circuit.

I want to know what Nwell was connected to, one port of caps/res. or VDD? which is better?
and can it connect to GND?
thanks!


The nwell is of course connected to vdd
I thinks It is not necessary to connect nwell to vdd.
How did you think it should be connected to vdd power supply?
 

where to put resistor in capacitor

your device may break down if nwell not connected to vdd..this is only for the potenetial measure
 

how to tell if this is a capacitor or resistor

Hi Guys:

I don't get it. What do you mean placing resistor and capacitor over NWELL and not in NWELL, does this mean like providing guard ring surrounding the resistor and connect it to Vdd or like placing a plane of NWELL over the resistor and capacitors.

Rgds
 

resistor and capacitor layout

hrkhari said:
Hi Guys:

I don't get it. What do you mean placing resistor and capacitor over NWELL and not in NWELL, does this mean like providing guard ring surrounding the resistor and connect it to Vdd or like placing a plane of NWELL over the resistor and capacitors.

Rgds

Poly/metal are over the nwell. Diffusions are in the nwell. It's just how the layout is fabricated.
 

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