I do not know what models you use but there are always parasitic resistances that are connected to supposedly floating nodes. So it is expected that when you open circuit the capacitor with the transmission gate, it will discharge in time. If you are asking for an error of uV per cycle when the transmission gate is always short circuited, it might be a settling issue caused by driving the capacitor via a resistance. Could you please run a longer simulation and see if this holds true?
The thing is when you reduce the resistance with larger transmission gates, the charge injection increases and you lose accuracy of uV's already. An optimization is necessary if this causes an error more than 1 LSB.
Also you are going to open and close that switch. Every time you do that you are going to charge a 5uF capacitor ,which is quite large to realize reliably in IC's by the way, this will increase your power consumption. I do not know speed specifications for your design but consider hybrid DAC's as another solution.
I hope this helps.