Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Capacitance Trend of a Varactor

Status
Not open for further replies.

tasctasc

Member level 1
Joined
Jul 13, 2011
Messages
40
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,589
When I simulate the capacitance of a varactor (nmos in an nwell) using spectre in cadence, the capacitance increases slightly with frequency. Other devices (standard NMOS and PMOS, MIM), the capacitance decreases with frequency which is expected. Is anyone able to please explain why the slight increase in varactor capacitance is seen with frequency. I have also noticed this trend in other papers but haven't been able to find an explanation.
Thank you.
 

Could you post you're simulation results and/or testbench?

Also are you sure you've connected the Nwell to ground (a common mistake!)?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top