Can't understand the concept of user defined attribute keyword used in VHDL

[reninroy]

i can't understand the concept of user defined attribute keyword used in the function calling, how it will generate the RTL diagram after synthsis. has any one talk about this topic.

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[FvM]

Re: VHDL

VHDL spec mentions:

Attributes of an actual are never passed into a subprogram: references to an attribute of a formal parameter are legal only if that formal has such an attribute. Such references retrieve the value of the attribute associated with the formal.

Can you give an example, what kind of attributes you mean regarding functions?