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Can't apply over 50 volts to h-bridge

muyil

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Hi Everyone,

I have been testing my inverter design recently. I tried to apply 150V to h-bridge as a bus voltage but it started to pull a lot of current and the 150V dropped down to 50 volts. The circuit doesn't pull much current below 50 volts. Why could this be happening? I am using ir2110 driver IC and didn't apply any dead time. Could this be the problem? If so, how can I solve that? It works well with the simulation as well.

Regards
 

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KlausST

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Hi,

not the best design. I see a lot of issues.

But I guess the overcurrent is caused by an inappropriate inductance.

Did you simulate it´s currents?
What´s the saturation current for the real device?

Klaus
 

muyil

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Hi,

not the best design. I see a lot of issues.

But I guess the overcurrent is caused by an inappropriate inductance.

Did you simulate it´s currents?
What´s the saturation current for the real device?

Klaus
Hi Klaus,

I didn't simulate it's current. I removed IR2110 which drives 50 khz signal to mosfets. Then I could manage to increase the dc bus voltage up to 340 volts. But when I removed IR2110 which drives 50 hz signal to mosfets, I had over current problem. It's the same problem when I test whole circuit. So I consider problem is due to 50 khz switching. But this happens only when I apply over 50 volts.
 

KlausST

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Hi,

your schematic seems to be from a simulation tool.
So it should be easy to simulate the current.

Dead time problem can be simulted, too. Just show draw the MOSFET currents of one half bridge in one chart.

But now I read thet there still is an overcurrent problem, when the IR2110 are removed. If so, where does the current flow? Due to the gate resistors all MOSFETS should be OFF then.

I still don´t know what inducatance you use. Please post a link to it´s datasheet.

Klaus
 

muyil

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Everything works fine with simulation. I can't measure the current passing through the mosfets. Simulation program doesn't allow me to do so. I removed output capacitor and inductor from pcb. Still has the same problem.
 

KlausST

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I removed output capacitor and inductor from pcb. Still has the same problem.
As long as the devices are not killed this is impossible.

Please show photos of both sides of the PCB with all the wiring.

Klaus
 

KlausST

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So,

I see no
* true GND plane
* bulk cap at the high voltage
* I see no fast decoupling cap at high side MOSFET drain.
* bulk capacitor for the 12V
* fast decoupling capacitor at each 12V pin of each IC, especially close to D3 and D4
* resonance suppression at the output LC filter
* noise suppression capacitor at the reference voltages
* sufficient isolation for the high voltage

This does not mean that the circuit fails from the first power ON. But it´s likely that one or more issues cause a fail at higher voltages. Maybe even kills your MOSFETs or your drivers.

The pictures are good, but I can´t follow the signals. It´s too complex and takes a lot of time.
Do you have PCB plots from your PCB software?

A power swtiching application is no simple application. It needs to take care of high voltages, high currents fast edges....

Klaus
 

KlausST

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Hi,

D3 and D4 are extremely overdimensionated. A small 1A schottky is more than sufficient. It won´t even get warm.
But they need to withstand your high voltage plus ringing. So in a good design a 200V type should be sufficient.
--> Because yours withstand 600V I see no problem.

Klaus
 

muyil

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Hi Klaus,

I added 1 ohm resistors under the half bridges to measure the current. The high frequency(50khz) side has current peaks up to 5.5A. On the other hand, the 50 hz side has no current peaks as it should, meaning they are never ON at the same time. So does this current peaks also mean both mosfets are ON some amount of time?
 

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muyil

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This is how it looks like on oscilloscope(real test). The output voltage of my push-pull converter drops down to 40VDC from 150VDC and supply voltage of the push-pull converter pulls 5A from power supply. So 60W is dissipated.
 

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FvM

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I added 1 ohm resistors under the half bridges to measure the current. The high frequency(50khz) side has current peaks up to 5.5A. On the other hand, the 50 hz side has no current peaks as it should, meaning they are never ON at the same time. So does this current peaks also mean both mosfets are ON some amount of time?
Sounds like a reasonable guess. The complementary LM339 topology provides some systematic dead time by asymmetrical propagation delay, but it may be dwarted by comparator offset voltage and delay variations. I'm not sure if too small dead time is the reason for the observed problems, but this can be best checked by increasing dead time.
--- Updated ---

Some post #7 schematic details don't look real, e.g. 75R + 100 nF "snubber". Due to variations between different schematics, I'm not sure which corresponds to the actual circuit.
 
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Easy peasy

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put reverse shottkies ( 35V 1A ) across the 10 ohm GD resistors to speed the turn off and give more dead time - most of your issues may well be RFI from the circuit as Vdd is increased - try upping the 10R to 47R and seeif things improve - make sure your mosfets are well heatsunk ....! - if the layout is poor the centre of the totem pole can go below gnd and really upset 2110 drivers ...
--- Updated ---

Also - your snubber caps are way too big, the leads on the electro's on the underside of the pcb should be as short as possible, there is no guarantee of suitable dead time with the gate drive generation circuitry ...
 

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