cannot synthesize simple mux with design compiler

pavel47 · May 21, 2010

Hello,

I have a problem when synthesizing multiplexer. This multiplexer has no inputs. Depending on control input it should output different constants. Something like this:

Code:

module MOD1 (S, OUT);
input S;
output [3:0] OUT;
assign OUT = (S == 1) ? 4'b0101 : 4'b1010;
endmodule

The result of synthesis is desastrous: everything is shorted.

Where is a problem ?

Thanks in advance.

Pavel.

P.S. employing always @(S) changes nothing

fcfusion · May 21, 2010

Try using this instead:

module MOD1 (S, OUT);
input S;
output [3:0] OUT;
wire [3:0] A;
wire [3:0] B;

assign A = 4'b0101;
assign B = 4'b1010;

assign OUT = (S) ?A : B;
endmodule

I simulated this way and it worked. Actually it should have worked with your code too. What program are you using?

pavel47 · May 21, 2010

Thank you for response,

Your code works in simulation as well as mine, but result of synthesis is the same.
For synthesis I use Synopsys Design Compiler 2008.
Maybe I must put some synopsys directive ...

In attachment I put schema - result of synthesis

user_asic · May 21, 2010

Can you provide your synthesis report?

pavel47 · May 21, 2010

The problem was in tool optimization. Now it's Ok. Thanks.

cannot synthesize simple mux with design compiler

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cannot synthesize simple mux with design compiler

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