Cannot generate ahdl_include in netlist by ADE

[daniellai]

dear ADE/verilogA experts,

I met a problem about the ADE compiler failed when simulating test circuit with verilog A macro.
And the problem is the generated netlist lost ahdl_include "***.va".

My simulation environment is:
a. Spectre/MMSIM10.0
b. ADE
c. The switch view includes: veriloga, ahdl

Please kindly advise if any comment, thanks.
Daniel Lai

 

[erikl]

May be your stop view list doesn't include ahdl -- or another view in the stop view list is found before the ahdl view?

 

[daniellai]

May be your stop view list doesn't include ahdl -- or another view in the stop view list is found before the ahdl view?

Hi erikl

Thanks for your reply.

The adhl and verilogA view were in switch view but not in stop view.
I confirmed the problem couldn't be solved after I added ahdl in stop view (and put in at the 1st).

(Actually, in some simulation environment, I also saw they don't have adhl in stop view but could generate ahdl_include "***.va" no problem.

 

[oldMan62]

If the view of your macro is "veriloga" then "veriloga" needs to be in the switch view list, not "ahdl". Or is this and "include" file?