I met a problem about the ADE compiler failed when simulating test circuit with verilog A macro.
And the problem is the generated netlist lost ahdl_include "***.va".
My simulation environment is:
a. Spectre/MMSIM10.0
b. ADE
c. The switch view includes: veriloga, ahdl
Please kindly advise if any comment, thanks.
Daniel Lai
The adhl and verilogA view were in switch view but not in stop view.
I confirmed the problem couldn't be solved after I added ahdl in stop view (and put in at the 1st).
(Actually, in some simulation environment, I also saw they don't have adhl in stop view but could generate ahdl_include "***.va" no problem.