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[SOLVED] Cannot find the design 'DW_ram_rw_s_dff' in the library 'WORK'.

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shedo

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Hi all,
I'm trying to synthesize the "DW_ram_rw_s_dff" from dw Block IP but I have this warning:

Warning: Cannot find the design 'DW_ram_rw_s_dff' in the library 'WORK'. (LBR-1)

I used the "DW_ram_rw_s_dff_inst" provided by Synopsys. This is my script:

Code:
set search_path {. ../src/hdl/rtl ../../90nm/snps}
set link_library {* saed90nm_typ.db}
set target_library {saed90nm_typ.db}

read_verilog {DW_ram_rw_s_dff_inst.v}
current_design DW_ram_rw_s_dff_inst

saif_map -start

link

#report_design_lib

create_clock [get_ports inst_clk]  -period 10  -waveform {5 10}
#

check_design

#ungroup -flatten -all

compile 

write_sdc ./DW_ram_rw_s_dff.sdc
write_file -format ddc -hierarchy -output DW_ram_rw_s_dff_synthesized.ddc
write -hierarchy -format verilog -output ./DW_ram_rw_s_dff.vg

write_parasitics -output ./DW_ram_rw_s_dff.spf

sh vcd2saif -input ../sim/rtlvcd.dump -output ./rtlvcd.saif

saif_map -create_map -source_instance tb/Ram -input ./rtlvcd.saif 
saif_map -write_map ./DW_ram_rw_s_dff_ptpxmap.tcl -type ptpx

report_power
exit

Synthesis log file: View attachment log.txt

I searched on google and I read the IP block manual but I can't find a solution. Can you help me?
 

sharath666

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"DW_ram_rw_s_dff_inst" uses a component "DW_ram_rw_s_dff" which the tool cannot find in either the link or target libraries.That is what it is complaining. Find out where it is defined. Then read that particular file.
 

shedo

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I tried to use the "DW_ram_rw_s_dff.v" component that I have found in "/synopsys/synthesis/H-2013.03-SP5-3/dw/sim_ver" but I have the same problem. :bang:


Code:
#set search_path {. ../src/hdl/rtl ../src/lib/snps ../src/sim}
#set link_library {* core_typ.db}
#set target_library {core_typ.db}

set search_path {. ../src/hdl/rtl ../../90nm/snps}
set link_library {* saed90nm_typ.db}
set target_library {saed90nm_typ.db}

[B]read_verilog {DW_ram_rw_s_dff.v DW_ram_rw_s_dff_inst.v}[/B]
current_design DW_ram_rw_s_dff_inst

saif_map -start

link

#report_design_lib

create_clock [get_ports inst_clk]  -period 10  -waveform {5 10}
#

check_design

#ungroup -flatten -all

compile 

write_sdc ./DW_ram_rw_s_dff.sdc
write_file -format ddc -hierarchy -output DW_ram_rw_s_dff_synthesized.ddc
write -hierarchy -format verilog -output ./DW_ram_rw_s_dff.vg

write_parasitics -output ./DW_ram_rw_s_dff.spf

sh vcd2saif -input ../sim/rtlvcd.dump -output ./rtlvcd.saif

saif_map -create_map -source_instance tb/Ram -input ./rtlvcd.saif 
saif_map -write_map ./DW_ram_rw_s_dff_ptpxmap.tcl -type ptpx

report_power
exit

Synthesis log file: View attachment log2.txt
 

sharath666

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The DFF component is not being read. Check your warnings. Read this file correctly
 

shedo

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Can you post an example of how to instantiate it properly?

Thanks for your help!
 

sharath666

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It is not a question of instantiation. You have to read the file correctly. Are you sure about the path of "DW_ram_rw_s_dff.v"? From the read_verilog command, it seems to me that the files are in the current working directory. Just confirm it once...
 

shedo

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Yes, I copied it from synopsys directory to current working directory. I have tried to simulate it with a tb and it worked perfectly.
 

oratie

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Check inside dc_shell your synthetic_library wariable. It should contains something like dw_foundation.sldb with path to this sldb library. Usually, this libray comes with DesignCompiler. Something like ./libraries/syn/dw_foundation.sldb

The DW_ram_rw_s_dff.v is for simulation only, not for synthesis. For synthesis, DC will use description from sldb file.
 

deepsetan

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Hi,

If you can't find it, just type manually "dw_foundation.sldb" and add it to your link libraries and synthetic library in application setup.
 

shedo

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Check inside dc_shell your synthetic_library wariable. It should contains something like dw_foundation.sldb with path to this sldb library. Usually, this libray comes with DesignCompiler. Something like ./libraries/syn/dw_foundation.sldb

The DW_ram_rw_s_dff.v is for simulation only, not for synthesis. For synthesis, DC will use description from sldb file.

That was the problem! Thanks!!! :-D

Code:
set search_path {. ../src/hdl/rtl ../../90nm/snps}

set target_library {saed90nm_typ.db}
set synthetic_library {dw_foundation.sldb}

set link_library "$target_library"
set link_library [concat $link_library $synthetic_library]


read_verilog {DW_ram_rw_s_dff_inst.v}
current_design DW_ram_rw_s_dff_inst
...

I have another question. I want to create a memory with 32bit of data_in and 8 bit of rw_addr. I read the DW_ram_rw_s_dff_inst, and I have a question about this piece of code:

Code:
`define bit_width_depth 8 // ceil(log2(depth))

Why do I have to use "ceil(log2(depth))" to calculate the bit_width_depth used to calculate the rw_addr width?

This is my edited code:

Code:
module DW_ram_rw_s_dff_inst(inst_clk, inst_rst_n, inst_cs_n, inst_wr_n,
                            inst_rw_addr, inst_data_in, data_out_inst );

  parameter data_width = 32;
  parameter depth = 256;
  parameter rst_mode = 0;
  `define bit_width_depth 8 // ceil(log2(depth)) 

  input inst_clk;
  input inst_rst_n;
  input inst_cs_n;
  input inst_wr_n;
  input [`bit_width_depth-1 : 0] inst_rw_addr;
  input [data_width-1 : 0] inst_data_in;
  output [data_width-1 : 0] data_out_inst;

  // Instance of DW_ram_rw_s_dff
  DW_ram_rw_s_dff #(data_width, depth, rst_mode)
    U1 (.clk(inst_clk),   .rst_n(inst_rst_n),   .cs_n(inst_cs_n),
        .wr_n(inst_wr_n),   .rw_addr(inst_rw_addr),   .data_in(inst_data_in),
        .data_out(data_out_inst) );
endmodule

The default values are:

Code:
parameter data_width = 8;
  parameter depth = 8;
  parameter rst_mode = 0;
  `define bit_width_depth 3 // ceil(log2(depth))

After calculating the formula provided it seems that I have to set parameter depth = 256 in order to have bit_width_depth 8.

Do you have any idea why?
 

oratie

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The depth means number of words. If you have two words (depth=2), you need only on addr bit to select the word. Agree? For 4 words (or 3 words) you need 2 bits. For 256 words (or for 255, 254...) you need 8 bits of addr. Nothing complicated.
 
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    shedo

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shedo

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Perfect, thanks alot for your help!
 

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