Design Compiler Graphical DC Ultra (TM) DFTMAX (TM) Power Compiler (TM) DesignWare (R) DC Expert (TM) Design Vision (TM) HDL Compiler (TM) VHDL Compiler (TM) DFT Compiler Library Compiler (TM) Design Compiler(R) Version H-2013.03-SP5-3 for RHEL64 -- Apr 08, 2014 Copyright (c) 1988-2013 Synopsys, Inc. This software and the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software is subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. Initializing... #set search_path {. ../src/hdl/rtl ../src/lib/snps ../src/sim} #set link_library {* core_typ.db} #set target_library {core_typ.db} set search_path {. ../src/hdl/rtl ../../90nm/snps} . ../src/hdl/rtl ../../90nm/snps set link_library {* saed90nm_typ.db} * saed90nm_typ.db set target_library {saed90nm_typ.db} saed90nm_typ.db read_verilog {DW_ram_rw_s_dff.v DW_ram_rw_s_dff_inst.v} Loading db file '90nm/snps/saed90nm_typ.db' Loading db file 'synopsys/synthesis/H-2013.03-SP5-3/libraries/syn/gtech.db' Loading db file 'synopsys/synthesis/H-2013.03-SP5-3/libraries/syn/standard.sldb' Loading link library 'saed90nm_typ' Loading link library 'gtech' Loading verilog files: 'Ram/src/hdl/rtl/DW_ram_rw_s_dff.v' 'Ram/src/hdl/rtl/DW_ram_rw_s_dff_inst.v' Detecting input file type automatically (-rtl or -netlist). Reading with Presto HDL Compiler (equivalent to -rtl option). Running PRESTO HDLC Compiling source file Ram/src/hdl/rtl/DW_ram_rw_s_dff.v Compiling source file Ram/src/hdl/rtl/DW_ram_rw_s_dff_inst.v Presto compilation completed successfully. Current design is now 'Ram/src/hdl/rtl/DW_ram_rw_s_dff.db:DW_ram_rw_s_dff' Loaded 2 designs. Current design is 'DW_ram_rw_s_dff'. DW_ram_rw_s_dff DW_ram_rw_s_dff_inst current_design DW_ram_rw_s_dff_inst Current design is 'DW_ram_rw_s_dff_inst'. {DW_ram_rw_s_dff_inst} saif_map -start Information: Building the design 'DW_ram_rw_s_dff' instantiated from design 'DW_ram_rw_s_dff_inst' with the parameters "32,8,0". (HDL-193) Warning: Cannot find the design 'DW_ram_rw_s_dff' in the library 'WORK'. (LBR-1) Warning: Unable to resolve reference 'DW_ram_rw_s_dff' in 'DW_ram_rw_s_dff_inst'. (LINK-5) Warning: Design 'DW_ram_rw_s_dff_inst' has '1' unresolved references. For more detailed information, use the "link" command. (UID-341) Information: The SAIF name mapping information database is now active. (PWR-602) 1 link Linking design 'DW_ram_rw_s_dff_inst' Using the following designs and libraries: -------------------------------------------------------------------------- * (2 designs) Ram/src/hdl/rtl/DW_ram_rw_s_dff_inst.db, etc saed90nm_typ (library) 90nm/snps/saed90nm_typ.db Information: Building the design 'DW_ram_rw_s_dff' instantiated from design 'DW_ram_rw_s_dff_inst' with the parameters "32,8,0". (HDL-193) Warning: Cannot find the design 'DW_ram_rw_s_dff' in the library 'WORK'. (LBR-1) Warning: Unable to resolve reference 'DW_ram_rw_s_dff' in 'DW_ram_rw_s_dff_inst'. (LINK-5) 0 #report_design_lib create_clock [get_ports inst_clk] -period 10 -waveform {5 10} Warning: Design 'DW_ram_rw_s_dff_inst' has '1' unresolved references. For more detailed information, use the "link" command. (UID-341) 1 # check_design Warning: Design 'DW_ram_rw_s_dff_inst' has '1' unresolved references. For more detailed information, use the "link" command. (UID-341) **************************************** check_design summary: Version: H-2013.03-SP5-3 Date: Tue Jun 30 17:33:48 2015 **************************************** Name Total -------------------------------------------------------------------------------- Inputs/Outputs 44 Multiply driven inputs (LINT-6) 44 -------------------------------------------------------------------------------- Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_clk' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_rst_n' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_cs_n' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_wr_n' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_rw_addr[7]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_rw_addr[6]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_rw_addr[5]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_rw_addr[4]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_rw_addr[3]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_rw_addr[2]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_rw_addr[1]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_rw_addr[0]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[31]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[30]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[29]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[28]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[27]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[26]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[25]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[24]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[23]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[22]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[21]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[20]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[19]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[18]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[17]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[16]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[15]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[14]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[13]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[12]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[11]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[10]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[9]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[8]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[7]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[6]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[5]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[4]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[3]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[2]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[1]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) Warning: In design 'DW_ram_rw_s_dff_inst', input port 'inst_data_in[0]' drives wired logic; the port direction may have been specified incorrectly. (LINT-6) 1 #ungroup -flatten -all compile Warning: Design 'DW_ram_rw_s_dff_inst' has '1' unresolved references. For more detailed information, use the "link" command. (UID-341) Information: Evaluating DesignWare library utilization. (UISN-27) ============================================================================ | DesignWare Building Block Library | Version | Available | ============================================================================ | Basic DW Building Blocks | H-2013.03-DWBB_201303.5 | * | | Licensed DW Building Blocks | | | ============================================================================ Information: There are 44 potential problems in your design. Please run 'check_design' for more information. (LINT-99) Beginning Pass 1 Mapping ------------------------ Processing 'DW_ram_rw_s_dff_inst' Information: Building the design 'DW_ram_rw_s_dff' instantiated from design 'DW_ram_rw_s_dff_inst' with the parameters "32,8,0". (HDL-193) Warning: Cannot find the design 'DW_ram_rw_s_dff' in the library 'WORK'. (LBR-1) Warning: Unable to resolve reference 'DW_ram_rw_s_dff' in 'DW_ram_rw_s_dff_inst'. (LINK-5) Updating timing information Information: Updating design information... (UID-85) Beginning Mapping Optimizations (Medium effort) ------------------------------- TOTAL ELAPSED WORST NEG SETUP DESIGN TIME AREA SLACK COST RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:00:02 6.3 0.00 0.0 0.0 0:00:02 6.3 0.00 0.0 0.0 0:00:02 6.3 0.00 0.0 0.0 0:00:02 6.3 0.00 0.0 0.0 0:00:02 6.3 0.00 0.0 0.0 0:00:02 6.3 0.00 0.0 0.0 0:00:02 6.3 0.00 0.0 0.0 0:00:02 6.3 0.00 0.0 0.0 0:00:02 6.3 0.00 0.0 0.0 0:00:02 6.3 0.00 0.0 0.0 0:00:02 6.3 0.00 0.0 0.0 0:00:02 6.3 0.00 0.0 0.0 Beginning Delay Optimization Phase ---------------------------------- TOTAL ELAPSED WORST NEG SETUP DESIGN TIME AREA SLACK COST RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:00:02 6.3 0.00 0.0 0.0 0:00:02 6.3 0.00 0.0 0.0 0:00:02 6.3 0.00 0.0 0.0 Beginning Area-Recovery Phase (cleanup) ----------------------------- TOTAL ELAPSED WORST NEG SETUP DESIGN TIME AREA SLACK COST RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:00:02 6.3 0.00 0.0 0.0 0:00:02 6.3 0.00 0.0 0.0 0:00:02 6.3 0.00 0.0 0.0 0:00:02 6.3 0.00 0.0 0.0 0:00:02 6.3 0.00 0.0 0.0 0:00:02 6.3 0.00 0.0 0.0 0:00:02 6.3 0.00 0.0 0.0 0:00:02 6.3 0.00 0.0 0.0 0:00:02 6.3 0.00 0.0 0.0 0:00:02 6.3 0.00 0.0 0.0 0:00:02 6.3 0.00 0.0 0.0 Loading db file '90nm/snps/saed90nm_typ.db' Optimization Complete --------------------- 1 write_sdc ./DW_ram_rw_s_dff.sdc Warning: Design 'DW_ram_rw_s_dff_inst' has '1' unresolved references. For more detailed information, use the "link" command. (UID-341) 1 write_file -format ddc -hierarchy -output DW_ram_rw_s_dff_synthesized.ddc Warning: Design 'DW_ram_rw_s_dff_inst' has '1' unresolved references. For more detailed information, use the "link" command. (UID-341) Writing ddc file 'DW_ram_rw_s_dff_synthesized.ddc'. 1 write -hierarchy -format verilog -output ./DW_ram_rw_s_dff.vg Warning: Design 'DW_ram_rw_s_dff_inst' has '1' unresolved references. For more detailed information, use the "link" command. (UID-341) Writing verilog file 'Ram/syn/DW_ram_rw_s_dff.vg'. 1 write_parasitics -output ./DW_ram_rw_s_dff.spf Warning: Design 'DW_ram_rw_s_dff_inst' has '1' unresolved references. For more detailed information, use the "link" command. (UID-341) Information: Writing parasitics to file 'Ram/syn/DW_ram_rw_s_dff.spf'. (WP-3) 1 sh vcd2saif -input ../sim/rtlvcd.dump -output ./rtlvcd.saif Error: VCD to SAIF translator version H-2013.03-SP5-3 Synopsys, Inc. direct mapping all VCD instances processing header of VCD file: ../sim/rtlvcd.dump error 0: Error: cannot open ../sim/rtlvcd.dump (aborting) Error: error reading vcd header Use error_info for more info. (CMD-013) saif_map -create_map -source_instance tb/Ram -input ./rtlvcd.saif Warning: Design 'DW_ram_rw_s_dff_inst' has '1' unresolved references. For more detailed information, use the "link" command. (UID-341) Error: Cannot find the SAIF file (./rtlvcd.saif). (PWR-201) 0 saif_map -write_map ./DW_ram_rw_s_dff_ptpxmap.tcl -type ptpx Warning: Design 'DW_ram_rw_s_dff_inst' has '1' unresolved references. For more detailed information, use the "link" command. (UID-341) Information: Writing SAIF name mapping information into the PT-PX name mapping file './DW_ram_rw_s_dff_ptpxmap.tcl'. (PWR-636) 1 report_power Information: Updating design information... (UID-85) Information: Propagating switching activity (low effort zero delay simulation). (PWR-6) Warning: Design has unannotated primary inputs. (PWR-414) Warning: Design has unannotated black box outputs. (PWR-428) **************************************** Report : power -analysis_effort low Design : DW_ram_rw_s_dff_inst Version: H-2013.03-SP5-3 Date : Tue Jun 30 17:33:51 2015 **************************************** Library(s) Used: No libraries used. Operating Conditions: TYPICAL Library: saed90nm_typ Wire Load Model Mode: enclosed Design Wire Load Model Library ------------------------------------------------ DW_ram_rw_s_dff_inst ForQA saed90nm_typ Global Operating Voltage = 1.2 Power-specific unit information : Voltage Units = 1V Capacitance Units = 1.000000ff Time Units = 1ns Dynamic Power Units = 1uW (derived from V,C,T units) Leakage Power Units = 1pW Cell Internal Power = 0.0000 uW (0%) Net Switching Power = 101.1061 nW (100%) --------- Total Dynamic Power = 101.1061 nW (100%) Cell Leakage Power = 0.0000 pW Internal Switching Leakage Total Power Group Power Power Power Power ( % ) Attrs -------------------------------------------------------------------------------------------------- io_pad 0.0000 0.0000 0.0000 0.0000 ( 0.00%) memory 0.0000 0.0000 0.0000 0.0000 ( 0.00%) black_box 0.0000 0.0000 0.0000 0.0000 ( 0.00%) clock_network 0.0000 0.1011 0.0000 0.1011 ( 100.00%) register 0.0000 0.0000 0.0000 0.0000 ( 0.00%) sequential 0.0000 0.0000 0.0000 0.0000 ( 0.00%) combinational 0.0000 0.0000 0.0000 0.0000 ( 0.00%) -------------------------------------------------------------------------------------------------- Total 0.0000 uW 0.1011 uW 0.0000 pW 0.1011 uW 1 exit Thank you...