You could find on internet some article about meta stability issue in electronic design. Two flip flops is a minimal to reduce dramatically the statistic to have an issue when a signal goes from one clock domain to another one clock domain.
Hello ..
Can metastability be avoided using fuzzy logic..
Can we afford transmission time delay of few microseconds to process the signal using fuzzy logic...
The discussion is about technics rather than semantics. It's called asynchronous, because it feeds the asynchronous reset input of registers. Although it's not a clocked signal, it needs to satisfy setup and hold timing requirements, otherwise the reset result will be unpredictable. This is usually achieved by releasing the reset synchronously to clock.
If you dont synchronize the asynchronous reset, how can you guarantee the reset signal can arrive at all registers within one clock cycle ?