Can you define these MOS netlists?

[hande.vinayak]

Hi to all,
I am having below given mos net lists, can anybody help me realize this...?,

1.What device does it interpret?
2.When can we use these?
3.What is the special in these devices which are form by MOS?

(drain gate source body)

Net lists..
1. in in in avdd pmos (in is an input pin)
2. on on on avss nmos (on is an input pin)
3. avdd avdd avdd avdd pmos
4. avss avss avss avss nmos
5. avss reference avss avss nmos (reference is a net)

Thnx.

 

[evilguy]

Hi to all,

1. in in in avdd pmos (in is an input pin)
2. on on on avss nmos (on is an input pin)
3. avdd avdd avdd avdd pmos
4. avss avss avss avss nmos
5. avss reference avss avss nmos (reference is a net)

Thnx.

3. and 4, the mosfet is short. i think if you simulate it, error will accure since the mosfet is all short. i dont think this circuit can be simulate.

-evilguy-

 

[hande.vinayak]

Hi,
But those mos acts as a dummy without affecting performance of the ckt.
Just comment abt other mos which are acting as a cap.
Thnx

 

[Blackuni]

hi,

yes you can they both will act as a voltage control caps individually but the problem is, i am unable to understand how you will connect this to a ckt to control the capacitance dynamically.

Can u give some info on where it is used?

Thanks

 

[hande.vinayak]

Yeah,
This I am using in PLL design.
Can you tell me what is difference between..

in in in avdd pmos

and

avdd in avdd avdd pmos ??

If both are forming cap then what is the significance of each?
Thnx

 

[Blackuni]

Hi,

Pmos cap have a edge over nmos counterpart for 1/f noise. If you use pmos cap along with n well will isolate bulk bias from other devices.


But upto my knowledge what the device might be(NMOS or PMOS) the connection will be some thing like

m1 node1 node2 node1 vdd pmos l=<> w=<>

node1 and node2 forms the terminals of mos cap. This config is suggested because it have more linear range compared to what you have defined. because this config will not have depletion mode of operation.

Hope this clears!

Thanks

 

[hande.vinayak]

Thnx a lot.

 

[startboy]

my dear:

first pmos and second mos like ESD protect device,

forth nmos is mos capacitor, thirth and fifth device like

current sink tank, thanks,





c.c.huang

Added after 2 minutes:

my dear:

first pmos and second mos like ESD protect device,

fifth nmos is mos capacitor, third and forth device like

current sink tank, thanks,





c.c.huang

 

[electronXwork]

hi to all,

my opinion is:

1. diode
2. diode
3 n 4. dummy
5. capacitor

 

[xiaorui2007]

hi to all,

my opinion is:

1. diode
2. diode
3 n 4. dummy
5. capacitor

I agree with you.
1,2 is a diode for ESD protection.
3,4 is a dummy mos for matching.
5 is a capacitor load for Vref that can keep Vref constant.

 

[sxunxs]

electronXwork is right...

 

[abhisheksbox]

Acording to me:----------

1. pmos will behave as diode connected load bcoz as gate and drain are short, and as gate and source is also short so it will be laways on.

2. nmos will never be on under this condition bcoz as gate and source r short so Vg-Vs = 0 which will be always less then Vt.

3. same as point1 at Vto.

4. again same as point 2 nmos will not work.

5. as drain and source r short and gate is at higher potential so it will work as capacitor.