Jun 26, 2005 #1 S sriramsv Junior Member level 1 Joined Mar 14, 2005 Messages 17 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,495 hi, is it possible to define 2 modules in the same page while coding in Modelsim.
Jun 27, 2005 #2 E echo47 Advanced Member level 6 Joined Apr 7, 2002 Messages 3,933 Helped 638 Reputation 1,274 Reaction score 90 Trophy points 1,328 Location USA Activity points 33,176 question in Verilog Do you mean "in the same file"? Yes. That works with any Verilog compiler.
Jun 27, 2005 #3 always@smart Full Member level 4 Joined Feb 8, 2002 Messages 195 Helped 15 Reputation 30 Reaction score 7 Trophy points 1,298 Location ASIA Activity points 2,027 Re: question in Verilog sriramsv said: hi, is it possible to define 2 modules in the same page while coding in Modelsim. Click to expand... yes you may use two module in same file/page, for example : module abc(a,b,c); //design module ... ... ... endmodule module tb_abc; //testbench ... ... ... endmodule hope this help regards, smart
Re: question in Verilog sriramsv said: hi, is it possible to define 2 modules in the same page while coding in Modelsim. Click to expand... yes you may use two module in same file/page, for example : module abc(a,b,c); //design module ... ... ... endmodule module tb_abc; //testbench ... ... ... endmodule hope this help regards, smart
Jun 27, 2005 #4 P pinu Newbie level 1 Joined Jun 25, 2005 Messages 1 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Location India Activity points 1,288 question in Verilog yes,possible,in top-down modelling or bottom up modelling.If u want details I can send it.
question in Verilog yes,possible,in top-down modelling or bottom up modelling.If u want details I can send it.
Jun 27, 2005 #5 N nanako Member level 5 Joined Jul 20, 2001 Messages 91 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 828 question in Verilog yes it is possible like module abc (.....); endmodule module def (....); endmodule module xyz (....); endmodule however when you compile for running you have to invoked the option -v file.v if not some of the modules might not be detected during compile for simulation.
question in Verilog yes it is possible like module abc (.....); endmodule module def (....); endmodule module xyz (....); endmodule however when you compile for running you have to invoked the option -v file.v if not some of the modules might not be detected during compile for simulation.
Jun 27, 2005 #6 S sriramsv Junior Member level 1 Joined Mar 14, 2005 Messages 17 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,495 Re: question in Verilog hi pinu, yeah i want those details. if u could send me that will be gr8